1. Field of the Invention
The present invention relates to techniques for delivering a signal in a semiconductor device and more particularly to an apparatus for delivering a signal, a memory device and method for precharging a memory device.
2. Description of the Related Art
A sense amplifier is used to determine the contents of a memory cell during a read operation (and in delivering signals between an external and internal core of a semiconductor device). The sense amplifier detects and amplifies relatively minute voltage or current levels of a signal that is to be transmitted through a pair of signal lines. For example in a memory device, the sense amplifier detects and amplifies a data signal of a memory cell, which is transmitted through a pair of bit lines, (a bit line and an inverted bit line). The sense amplifier is used to amplify voltage coming off bit line and an inverted bit line.
To operate the sense amplifier, an input unit of the sense amplifier and the pair of signal lines typically have to be precharged to a known or nominal voltage level. Voltages of the signal line and the inverted signal line in the precharged pair of signal lines are made equal to each other through the precharge operation.
FIG. 1 is a circuit block diagram of a conventional connection circuit for precharging pairs of bit lines and a sense amplifier in a conventional SRAM 100.
A static random access memory (SRAM) that has its own amplifying function in a memory cell does not require a sense amplifier with respect to each of pairs of bit lines. However, a dynamic random access memory (DRAM) does not have its own amplifying function within each memory cell, and thus requires a sense amplifier.
Referring to FIG. 1, pairs of bit lines respectively coupled with first column memory cells 111, second column memory cells 112, and Nth column memory cells 11N are commonly connected to a single sense amplifier 150 through a multiplexer 140.
For example, the multiplexer 140 includes a first switching unit 141, a second switching unit 142, and an Nth switching unit 143. The first switching unit 141 is connected to a first pair of bit lines including bit line BL1 and inverted bit line /BL1 The second switching unit 142 is connected to a second pair of bit lines including bit line BL2 and inverted bit line /BL2. The Nth switching unit 143 is connected to an Nth pair of bit lines including bit line BLN and inverted bit line /BLN.
Each of the plurality of N switching units (141, 142 . . . 143) is activated by a logic low (active low) switching signal. When a first switching signal SW_EN1 is at the logic low voltage level, the first switching unit 141 connects the first pair of bit lines to the sense amplifier 150. When the first switching signal SW_EN1 is at a logic high voltage level, the first switching unit 141 disconnects the first pair of bit lines from the sense amplifier 150. When the second switching signal SW_EN2 is at the logic low voltage level, the second switching unit 142 connects the second pair of bit lines to the sense amplifier 150. When the second switching signal SW_EN2 is at a logic high voltage level, the second switching unit 142 disconnects the second pair of bit lines from the sense amplifier 150. When the Nth switching signal SW_ENn is at the logic low voltage level, the Nth switching unit 143 connects the Nth pair of bit lines to the sense amplifier 150. When the Nth switching signal SW_ENn is at a logic high voltage level, the Nth switching unit 143 disconnects the Nth pair of bit lines from the sense amplifier 150.
In a read/write operation period (i.e., an active period or a transmission period), the multiplexer 140 selects a pair of bit lines and connects the selected pair of bit lines to the sense amplifier 150. For example, when the first switching signal SW_EN1 is at the logic low voltage level, and the second switching signal SW_E N2 and the Nth switching signal SW_ENn are at the logic high voltage level, the multiplexer 140 connects only the first pair of bit lines BL1 and /BL1 to the sense amplifier 150.
A precharge control signal PRECH_EN is activated at the logic low voltage level within a preparatory period, and inactivated at a logic high voltage level within the transmission period.
Within the preparatory period (before a read/write operation period), the plurality of N precharge units (101, 102 . . . ON) precharge the plurality of N pairs of bit lines (BL1 and /BL1, BL2 and /BL2, . . . BLN and /BLN), respectively. Also, each precharge unit among the N precharge units (101, 102, . . . 10N), when selected, precharges an input unit of the sense amplifier 150.
FIG. 2 is a circuit diagram of a multiplexer control unit 200 that generates switching signals for the multiplexer 140 in FIG. 1.
The multiplexer control unit 200 generates the N switching signals SW_EN1, SW_EN2 and SW_ENn by just inverting a corresponding column address signal (Y-ADD1, Y-ADD2 . . . Y-ADDn) or a decoded signal of the column address signal. Therefore, the multiplexer control unit 200 may consist entirely of N inverters 210, 220 to 230.
During a readwrite operation period, the output signal of only one of the inverters among the N inverters (210, 220, to 230) is at the logic low voltage level, output signals of the other inverters are at the logic high voltage level.
Referring back to FIG. 1, when the first pair of bit lines BL1 and /BL1 is connected to the sense amplifier 150 in response to the N switching signals from the multiplexer control unit 200, the input unit of the sense amplifier 150 is precharged by the first precharge unit 101.
FIG. 3 is a timing diagram illustrating a process of precharging the input unit of the sense amplifier 150 in FIG. 1.
Referring to FIG. 3, FIG. 3 shows the changes of voltage levels of a word line control signal 310, the precharge control signal 320, a bit line signal 330, a sense amplifier control signal 340, switching signals 350 and 360, and a signal 370 of the input unit of the sense amplifier.
When the word line control signal 310 is at the logic high voltage level, data stored in a memory cell connected to the selected word line is provided to the pairs of bit lines. The voltage level of each of the bit line signals (e.g., on BL1 and /BL1) 330 depends upon the stored data in the memory cell. When the voltage level signal 330 on one of the bit lines (e.g., on BL1 and /BL1) is varied, the voltage level of the signal 370 of the input unit of the sense amplifier is also varied.
However, when the word line control signal 310 is at the logic high voltage level, the precharge control signal 320 is at the logic high voltage level, when the precharge control signal 320 is at the logic high voltage level, at N of the N precharge units (101, 102, . . . 10N in FIG. 1) are disconnected from the pairs of bit lines.
When the voltage level of the signal 370 of the input unit of the sense amplifier is changed to a predetermined level, the sense amplifier control signal 340 becomes logic high and thus the sense amplifier operates. Therefore, the voltage level of the signal 370 of the input unit of the sense amplifier is rapidly changed. However, when the sense amplifier control signal 340 is at the logic high voltage level, because the switching signal SW_EN 350 of the selected pair of bit lines is at the logic high voltage level, the selected pair of bit lines is disconnected from the input unit of the sense amplifier 150. Meanwhile, the switching signal 360 of the unselected pair of bit lines maintains (the precharged) logic high voltage level. The output signal 370 of the input unit of the sense amplifier is outputted to an external device.
After the output signal 370 of the input unit of the sense amplifier is outputted to the external device, the sense amplifier control signal 340 and the switching signal 350 of the selected pair of bit lines become logic low. At this time, the precharge control signal 320 is at the logic low voltage level. Thus, the input unit of the sense amplifier 150 is precharged through the selected pair of bit lines.
In the conventional precharge method, precharging the input unit of the sense amplifier requires a relatively long time as illustrated in a dotted circle A, because the one precharge unit that is connected to the selected pair of bit lines precharges the input unit of the sense amplifier.
FIG. 4 is a circuit block diagram illustrating another example of a conventional connection circuit for precharging pairs of bit lines and a sense amplifier in a conventional SRAM 400.
First column memory cells 111, second column memory cells 112, Nth column memory cells 11N, pairs of bit lines, a multiplexer 440 including switching units 141, 142 and 14N, precharge units 101, 102, and 10N, and a sense amplifier 450 have the same structure and perform the same function as described with respect to FIG, 1, and thus repeated descriptions are omitted.
The SRAM 100 in FIG, 1 differs from the SEAM 400 in FIG. 4 by additionally including a distinct local precharge unit 460 for precharging the input unit of the sense amplifier 450, and a local precharge control unit 470 for controlling the local precharge unit 460.
When the local precharge control signal LPRECH_EN is at the logic low voltage level, the local precharge unit 460 precharges the input unit of the sense amplifier 450. The local precharge control unit 470 generates a local precharge control signal LPRECH_EN based upon the precharge control signal PRECH_EN and the sense amplifier control signal SENSE_EN. When the precharge control signal PRECH_EN is at the logic high voltage level or the sense amplifier control signal SENSE_EN is at the logic high voltage level, the local precharge control signal LPRECH_EN is at the logic high voltage level, otherwise the local precharge control signal LPRECH_EN is at the logic low voltage level.
FIG. 5 is a timing diagram illustrating a process of precharging the input unit of the sense amplifier in FIG. 4.
FIG. 5 illustrates changes of voltage levels of a word line control signal 510, a precharge control signal 520 a bit line signal 530, a sense amplifier control signal 540, switching signals 550 and 560, a signal 570 of the input unit of the sense amplifier, and a local precharge control signal 580.
When the word line control signal 510 is at the logic high voltage level, data stored in a memory cell connected to the selected word line is provided to the pairs of bit lines. The voltage level of the bit line signal 530 is varied according to the stored data in the memory cell. When the voltage level of the bit line signal 530 is varied, the voltage level of the signal 570 of the input unit of the sense amplifier is also varied. However, when the word line control signal 510 is at the logic high voltage level, the precharge control signal 520 is at the logic high voltage level. When the precharge control signal 520 is at the logic high voltage level, all N of the N precharge units 101, 102 and 10N are disconnected from the pairs of bit lines.
When the voltage level of the signal 570 of the input unit of the sense amplifier is changed to a predetermined level the sense amplifier control signal 540 becomes logic high, and thus the sense amplifier operates. Therefore, the voltage level of the signal 570 of the input unit of the sense amplifier is rapidly varied. However: when the sense amplifier control signal 540 is at the logic high voltage level, because the switching signal 550 of the selected pair of bit lines is at the logic high voltage level, the selected pair of bit lines is disconnected from the input unit of the sense amplifier. The switching signal 560 of the unselected pair of bit lines maintains the (precharged) logic high voltage level. The signal 570 of the input unit of the sense amplifier is outputted to an external device.
After the signal 570 of the input unit of the sense amplifier is outputted to the external device, the sense amplifier control signal 540 and the switching signal 550 of the selected pair of bit lines become logic low. At this time, the precharge control signal 520 is at the logic low voltage level. Thus, the input unit of the sense amplifier is precharged through the selected pair of bit lines.
When the sense amplifier control signal 540 is at the logic low voltage level, the local precharge control signal 580 is also at the logic low voltage level and thus the local precharge unit precharges the input unit of the sense amplifier.
Because the input unit of the sense amplifier is precharged by using the local precharge unit as well as the precharge unit that is connected to the selected pair of bit lines, precharging the input unit of the sense amplifier requires a relatively short time as illustrated in a dotted circle B.
Because the SRAM 400 in FIG. 4 further includes the local precharge unit 460 and the local precharge control unit 470, size of the chip is increased. Thus, the precharging circuit in FIG. 1 can be applied to a large scale integration (LSI) SRAM, and the precharging circuit in FIG. 4 can be applied to a small scale integration (SSI) SRAM.
Memory devices included in modern multimedia, communications and computing applications need to have high capacity and a high operation speed. Thus, a precharging circuit that performs a fast precharging operation for a high speed memory and that can be integrated in a small area is desirable.